CRIO-WR is based on a Spartan-6 FPGA with WR PTP Core plus the required hardware to implement a standalone WR node (see also White Rabbit Node Reference Design for more information).
The backplane connector, a dedicated power supply with sleep-mode, a separate EEPROM for module identification parameters and an SPI plus some glue logic in the FPGA’s CRIO User Core are used for CompactRIO functionality. The connector at the front panel provides 10 user I/O signals, each protected by a TVS. The I/Os are programmable depending on the application requirements (input / output, 3.3V / LVDS, ISERDES2, OSERDES2, IODELAY2 etc.). The 4 LEDs at the front panel are user programmable, e.g. as status indicators.