cRIO-WR

CompactRIO White Rabbit Module

WR node in CompactRIO format
Complies with most CompactRIO specifications (see OHWR website)
Standalone WR operation (GrandMaster, Master or Slave mode)
10 MHz and PPS inputs (GrandMaster mode)
125 MHz and PPS outputs
6-layer PCB
On-board power supply
– 5 V input from CompactRIO carrier
– 3.3 V and 1.2 V output
– Sleep mode
Clocking resources (used by WRPC)
– 1x TCXO 25 MHz controlled by a DAC
– 1x VCXO 20 MHz controlled by a DAC
– 1x low-jitter frequency synthesizer/fanout with fixed configuration, Fout=125 MHz
1x Xilinx Spartan-6 FPGA (XC6SLX45T-3FGG484C)
1x SPI FLASH 32 MBit (M25P32-VMF6P)
1x Temperature sensor with unique ID (optionally used by WRPC)
1x EEPROM 64 kbit (optionally used by WRPC)
1x EEPROM 16 kbit (cRIO)
FPGA configuration from SPI FLASH or via JTAG
Front panel
– 1x SFP cage for fibre-optic transceiver (WRPC)
– 1x Connector mini USB B (USB-UART bridge, WRPC user shell)
– 1x Connector HDSUB-15 (user programmable I/O, up to 10x 3.3V / 5x LVDS)
– 4x LEDs (user programmable)
On-board add-ons
– 1x Push button (user programmable)
– 2x LEDs (user programmable)
– 2x LEDs (power on, power good)

Full technical documentation can be found here

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Description

CRIO-WR is based on a Spartan-6 FPGA with WR PTP Core plus the required hardware to implement a standalone WR node (see also White Rabbit Node Reference Design for more information).
The backplane connector, a dedicated power supply with sleep-mode, a separate EEPROM for module identification parameters and an SPI plus some glue logic in the FPGA’s CRIO User Core are used for CompactRIO functionality. The connector at the front panel provides 10 user I/O signals, each protected by a TVS. The I/Os are programmable depending on the application requirements (input / output, 3.3V / LVDS, ISERDES2, OSERDES2, IODELAY2 etc.). The 4 LEDs at the front panel are user programmable, e.g. as status indicators.

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