Fine delay

4 channel FMC fine delay module

1 trigger input, 4 outputs
Trigger level TTL, outputs capable of driving a 50 Ohm load, > 2 V/ns slew rate
Operation modes: Pulse delay, Singel channel, Pulse generator
Maximum input pulse rate: 2MHz (minimum pulse spacing 50ns)
Output pulse width: 50 ns – 1 s (10 ps resolution)
Output pulse spacing 100 ns – 1 s (10 ps resolution)
Output pulse repeat count (train generation) 1 – 65536 pulses or infinity (continuous mode)
Onboard timebase accuracy ± 4ppm, Cesium-quality accuracy will be reached when used on a White Rabbit enabled FMC carrier
TDC Resolution 28 ps
TDC Precision (std. dev) 55 ps
Accuracy ± (300 ps + timebase accuracy)
Time tag buffer 1024-entries circular buffer with time tags for input/output pulses. Buffer interrupt (with timeout/threshold coalescing)
Full technical documentation can be found here


The FMC DEL 1ns 4cha delay module is a mezzanine card according the FMC (FPGA Mezzanine Card) standard and will take in a TTL trigger signal and will send it out to four different outputs. The delay from the trigger input to each of the outputs can be set independently in a range from 500 ns to 120 seconds. It is implemented using a dedicated time-to-digital converter.

Modes of operation:
Pulse delay: a pulse coming to the input triggers generation of a pulse or series of pulses of given width and repetition rate on chosen outputs after a certain time programmed by the user (see fig. 1a).
Single channel TDC: time tags of incoming pulses are provided to the user via a circular buffer.
Pulse generator: produce a pulse or a series of pulses of arbitrary length and repetition rate starting at a given UTC/TAI time

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